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The AI Revolution has created a huge demand for processing power to train Frontier Models, which NVIDIA is filled with GPU at its high end. But the sudden AI diagnosis and agent AI in 2025 is exposing the difference in the memory pipeline, which De Metrix expects its latest 3D digital in memory will address the computement (3 DIMC) architecture, which is shown on hot chips this week.
Even before the launch of the Chat GPT at the end of 2022, before provoking the AI revolution, the people of the D -Matrix already pointed out a major need for large and fast memory in response to large language models (LLM). Sid Sheath, the CEO and co -founder of the D -Matrix, was already predicting the OII -Incration workload so that the Open AI and Google -affiliated LLMS, which were already turning the AI world and beyond.
“We think it will continue for a long time,” said Shith. Big Datawire About the ability to change LLM in April 2022. “We think people will mandate gravity around the transformers for the next five to 10 years, and it will be a burden to work work for the AI computing for the next five to 10 years.”
The sheet not only properly predicted the impact of the transformer model change, but it also predicted that it would eventually result in an increase in the burden of AI. It offered a business opportunity for sheet and DM matrix. The problem was that GPU -based high -performance computing architectures that always worked well for the training of the Bigger LLM and Frontier Model were not ideal for operating AI -in conference workload. In fact, the D -Matrix pointed out that the problem has increased the drum all over the way, which cannot be effectively transmitted to the data, which is required to support the high -speed AI’s workload.
Memory growth increases
The solution to this de -matrix was to focus on innovation in the memory layer. Although Dram AI could not maintain the requirements of the diagnosis, a sharp and expensive form of memory called Sram, or static access memory, is ready for this work.
The D -Matrix used the Digital in Memory Computing (DMIC) technology that turned a processor directly into SRAM modules. Its knight hawk architecture embedded DMIC chapels directly on SRAM cards, which is a straightforward plug on PCI bus, while its J. Hawk architecture provided a dye -to -die offer for scale out processing. Both of these architectures were included in the company’s flagship offer, named Corrier, which today uses the latest PCIE gene 5 form factor and features high memory bandout of 150 TB/second.
In 2025, there were many predictions of the sheet. We are firmly in the middle of a major change in the diagnosis of AI with AI training, agent AI has developed to invest heavily in the years to come. D -Matrix has worked according to the emerging AI burden, and this week has announced that its next generation of pow hawk architecture, which uses three -dimensional stacked DMIC technology (or 3DMIC), is now working in the lab.
Sheath is convinced that 3dmic AI estimates will promote performance to help pass through the memory wall.
The Sheth wrote in the LinkedIn blog post, “Not just flop, AI is estimated by memory. Models are growing rapidly and traditional HBM memory systems are very expensive, electric hunger and bandout limited.” “3 Demk changes the game. By stacking memory in three dimensions and bringing it into severe integration with computers, we reduce dramatic delays, improve bandout, and unlock the new benefits of performance.”
De-Matrix’s new Pohak architecture supports 3dmic technology (Image Source D-Matrix)
The memory wall has been growing for years, and this is due to the progress of memory and processor technologies. The founder and CTO of De Metrix Swedep Bhuja shared this week in a blog post, “Industry benchmark shows that computing performance has increased by about 3x every two years, while the memory bandout is behind only 1.6x.” “The result is a wider difference where the valuable processors sit useless, looking forward to the arrival of data.”
Bhuja wrote that although it would not completely close the space with the latest GPU, the 3DMIC technology promises to close the gap. Since the Pew Hawk comes in the market, the company is currently developing the next generation of memory processing architecture that uses 3dmic, dumb repeat.
Bhuja wrote, “Ripter… will add 3DIMC to its design – we will take advantage of what we and our Gahak learning from Pew Hawk.” “By stacking memory vertically and firmly connecting with the computing chapels, the repeat has promised to break the memory wall and operate completely new levels of TCO.”
How much better? According to Bhuja, AI with 3DIMC compared to D -Matrix HBM4 is expecting 10x better memory bandout and 10x better energy efficiency while running 3DIMC.
Bhuja wrote, “These are not the additional benefits. By putting memory requirements in our design center – from the courser to the Ripter and beyond – we are making sure that its measurement is fast, more affordable and sustainable.
This article first appeared on our sister’s publication, Big Datawire.
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